phyFLEX® represents the evolution of the Phytec System on Module concept. Its innovation is the fusion between the scalability and compatibility of the phyCARD® and the phyCORE®’s individualized support of processor interface functionality.
The phyFLEX®, like the phyCARD®, provides for 100 percent hardware compatibility due to standardized break-out of interface signals to defined pins on the first of its three external connectors. This connector breaks out nextgen interfaces supported by advanced ARM Cortex-A family processors that are common to advanced embedded applications: such as PCI Epxress, SATA and USB 3.0. The phyFLEX® provides access to remaining functions of underlying processor across two optional connectors.
High-performance embedded systems are based on cutting-edge microprocessors. Hardware design around these devices is progressively more challenging. At the same time, development cycles and life spans for these new processors are even shorter. This has greatly increased time-to-market pressure on embedded developers in regards to both hardware and software design.
The innovative fusion of scalability and future-proof compatibility render the phyFLEX® a solution to the challenges presented by design around cutting-edge embedded processors.
The phyFLEX® provides three plug-in connections between the module and the main circuit board. Depending on the kind of application, it is possible to use just one (or two, or all three).
Connector 1 (The MUST-HAVE signals, standardized).
All the signals that are supported by every phyFLEX® are handled by this connector.
Connector 2 (If supported by the controller, standardized).
These signals on this connector are also standardized. However, they are only made available if the particular controller offers this interface.
Connector 3 (Makes the phyCARD® into a phyCORE®).
All the special features of a controller are made available here for possible use.
Connector 1 on the phyFLEX® provides compatibility via specifically defined, standardized signals such as Ethernet, USB-Host and USB-OTG. PCI Express is the only exception to this standardized pin assignment, as support of this function is depending on whether PCI Express is available on the underlying processor. When populated with the optional connectors 2 and 3, the phy-
FLEX® provides the same level of expansive processor-specific interface support offered by the phyCORE®.
Connector 2 offers additional signals — again at predefined pins — that are common to many embedded applications, such as CAN.
Connector 3 is the wildcard that offers remaining, nonstandard functions of the underlying controller. With the phy-FLEX®, according to cost requirements and technical needs of an application end users can flexibly choose between:
• 100% scalability and compatibility between phyFLEX® modules: one connector
• Partial scalability and compatibility across phyFLEX® SOMs and / or access to a subset of all processor features: two connectors.
• Maximum access to processor-specific features: three connectors