The MPC5xxx core belongs to the class of 32 bit RISC processors from the PowerPC family. It was designed by NXP mainly for automotive and industrial systems and represents a SoC with a speed of up to 600 MHz and is therefore suitable for embedded applications.
The e200 is derived from the MPC5xx family and uses the Power ISA v.2.03 and the older Book E specifications. The e200 SoCs follow the MPC55xx and MPC56xx / JPC56x naming scheme.
The e200z7 has a 10-stage double superscalar instruction pipeline with a unit for branch prediction, a 2-entry MMU, a SIMD-capable FPU and a combined 32 KiB L32 cache. Just like its predecessor, it uses all commands of the Power ISA and the VLE specification and is also connected via a two-channel AMBA bus.