phyCORE^®-i.MX 8M Plus FPSC
Arm^® Cortex^®-A53/-M7

Based on the NXP i.MX 8M Plus SoC from NPX Semiconductors, the phyCORE-i.MX 8M Plus is the "smartest" PHYTEC module. It will be available in 2024 versions from 3: As a DSC soldering module, as a plug-in module and as a standard module in the FPSC variant.

Equipped with up to 4 Cortex-A53, a Cortex-M7 for real-time applications, as well as a unique combination of a variety of multimedia interfaces with a powerful NPU (Neural Processing Unit), the phyCORE-i.MX 8M Plus is ideal for machine learning (ML), image processing, advanced multimedia and industrial IoT applications.

The scalable and size-optimized phyCORE-i.MX 8M Plus is the perfect basis for using all the i.MX 8M Plus functions in areas where intelligent and fast processing of multimedia data in the smallest space is required. Be it in the smart home (e.g. home automation), the smart city (e.g. people/traffic monitoring), Industry 4.0 (e.g. intelligent robot control, HMI) or IIoT applications (e.g. edge computing). The FPSC variant is particularly attractive: It is size-optimized and has a sophisticated anchor soldering technology for maximum production yield. Thanks to the FPSC design, the phyCORE-i.MX 8M Plus FPSC is compatible with all existing and future modules of the FPSC 24.0 standard.

With the phyCORE-i.MX 8M Plus, the necessary, highly complex parts of the circuit design have already been completed, which enables simple and cost-effective application development and significantly reduces the time to market.

What is FPSC? 

It offers a size and cost-optimized footprint that guarantees a particularly high production yield thanks to stable anchor solder connections. FPSC modules have a unique pinout that is divided into three compatibility zones:

1. Must-have signals
2. Preferred Signals
3. Proprietary Signals

This structure enables the use of current and future processor features without compromising on standardization. FPSC allows scalable performance and cost-efficient carrier board design through staggered pins and optimized pinout routing.